When debugging AOI inspection programs, we must never focus solely on the parameter sliders in the software interface; we must simultaneously retrieve NG images, manual re-inspection records, and Solder Paste printing consistency data for the same work order from the past three days. If the image brightness threshold is set too high, tiny solder balls will be filtered out, while if it is set too low, PCB substrate texture will be misjudged as bridging defects. This contradiction is particularly prominent when the JJY AOI inspection system processes OSP surface boards.

The setting of the minimum recognition area must match the main package size of the current production line. For example, when applying a 0.3mm² lower limit to 0201 resistor solder joint inspection, if the lens distortion coefficient is not calibrated synchronously, the normal offset solder paste edge will be judged as an open circuit, while the existing micro-short circuit will be directly missed due to its area being slightly below the threshold. This situation is particularly prone to occur when using 15X optical magnification with dual-source alternating lighting.

The edge sharpness parameter must be adjusted in conjunction with squeegee pressure and stencil aperture accuracy. When the solder paste printing height variation coefficient exceeds 12%, simply increasing sharpness will only amplify the jagged edge noise caused by squeegee wear, instead reducing the sensitivity of AOI inspection to real cold solder joints. We once found that the missed report rate suddenly increased by 3.7% after switching to a new batch of stencils, and finally located that the edge gradient sampling step in the AOI inspection software was not compensated correspondingly with the change of stencil thickness.

The angle tolerance must be set in tiers according to device type. QFP device pin coplanarity allows a deviation of ±2°, but SOIC devices can only be given ±0.8°. If uniformly set to ±1.5°, it will cause QFP pin lifting that should trigger an alarm to escape detection, while being overly sensitive to slight flipping of SOIC pins. The frequency of such misjudgments increases significantly when the reflow oven temperature zone fluctuates by ±3℃.

After each parameter modification, full real-board verification for two standard shifts must be run. We cannot only look at the first article OK rate, but must count the number of similar defects captured in 200 consecutive boards and the consistency rate with manual re-inspection, especially paying attention to hidden dangers such as BGA bottom bridging that cannot be visually inspected. Because the JJY AOI inspection relies on X-ray fusion images, if the X-ray tube voltage calibration file is not updated synchronously, no matter how fine the visual parameters are, they cannot suppress the risk of missed reports of underlying cold solder joints.